Hello everyone,
I’ve been reviewing the guide posted here:
Darkn | Properly Bypassing The Tsunami (v114+)
It suggests bridging pin 3 (WP) and pin 8 (VCC) on the SPI flash chip (Winbond 25Q128JWPM) as a way to disable firmware write protection in order to run SH1MMER utilities on ChromeOS v138+.
I’m specifically working with a Lenovo 100e Chromebook Gen 3, codename zork/vilboz, and I have strong concerns regarding the safety of this procedure on this model — particularly due to the presence of Google’s CR50 security chip.
From my understanding:
The CR50 monitors SPI access and enforces firmware write protection policies.
Applying a physical short between WP and VCC while the CR50 is active might cause unexpected current draw, risking permanent damage to either the flash chip or the CR50 itself.
Some users have reported boot loops or dead boards after improper bridging — even when precautions like battery disconnection were followed.
Has anyone here successfully attempted this bridging method on vilboz (Zork) devices?
Is there a safer alternative that avoids direct hardware tampering?
I’d appreciate any insights, especially regarding CR50’s tolerance to this kind of manipulation or whether there are model-specific risks for Vilboz. My goal is to avoid permanently bricking a functional device just to bypass enterprise enrollment.
Thanks in advance!
— Samuel