Slow boot on Acer Chromebox CXI4 (kaisa) and Asus Chromebox 4 (duffy)

[Ryzo]

could it be a almost dead cmos battery?

[MrChromebox]

maybe? it shouldn’t though.

[cydox]

related side-question:

How does a CMOS clear work on “modern consumer“ mainboards?

If I understand correctly on Chromebooks, information like memory training data is stored in SMMSTORE on the SPI flash. I assume this is the same on consumer mainboards, right? Or do they actually have a separate CMOS chip?

So if you remove all power including the CMOS battery, this information is not lost automatically. Is the firmware on next power-up purposefully clearing information from SPI flash in order to emulate behavior of CMOS?

The behavior is certainly like this on my AM5 board. If I remove power (including the button cell), all firmware settings are restored to default and the first boot takes ages for the DDR5 memory training.

[MrChromebox]

@cydox

If I understand correctly on Chromebooks, information like memory training data is stored in SMMSTORE on the SPI flash. I assume this is the same on consumer mainboards, right? Or do they actually have a separate CMOS chip?

memory training data is cached on the SPI flash chip, where is arbitrary. coreboot uses one or more MRC_CACHE regions. SMMSTORE is used only for UEFI NVRAM.

CMOS is used for RTC and that’s about it

some (non-ChromeOS) devices might store a NVRAM hash in CMOS and invalidate their NVRAM settings if the CMOS is cleared / hash is cleared.